This board lives in the dewar electronics box and was designed to receive the umbilical cable from the CCD controller and provide isolation of the bias voltages from the CCD chip in the dewar. The board contains six DG411 quad analog switches, two transistors, two optical isolators, and various filter and bypass capacitors.

Sheet 1

The first page of the schematic shows that 61-pin connector P1 that receives the umbilical cable from the CCD controller on the left-hand side. On the right-hand side is the power input connector P2. The power is divided into two sections, the 5 volt logic (digital) supply and the +/- 16 analog supplies. These supplies are isolated from each other to lessen noise on the bias voltages. Also shown is the ANALOG_SW_EN signal arriving on pin 3 of P2. R1 is used as a pull-up for the ANALOG_SW_EN signal. Along the bottom of the sheet is the filtering and bypassing component for the +/- 16 volt supplies.

Sheet 2

This sheet has two columns of analog switches. In each case, a clock signal is presented to the input of a switch and the resulting signal has OUT appended to its name. All of the clocks are pulled down to ground so that if a cable is disconnected or a wire breaks the output of that particular switch won’t have a potentially harmful voltage on it’s output that is connected directly to the CCD chip. As is shown on the schematic, each of the clock lines also has a small filtering/bypass capacitor on it’s output. These switches are all enabled by the ANALOG_SW_EN signal. This enable signal allows the computer to set the clock waveforms as needed before they are allowed to go to the CCD chip. This way we can insure that no incorrect levels are applied to the chip during that time it takes to load the waveforms.

Sheet 3

This sheet shows the bias voltages that go to the CCD chip. On the right-hand side are the RD (reset Drain) and OPG (output gate) levels. There are two each of these signals used for a two-amplifier CCD chip. Note that these signals are held at DC levels and therefor have more filtering on the outputs. On the left-hand side of the sheet are the VDD, SUB, and Guard signals. The SUB (substrate) and Guard (guard ring) levels are again presented to an analog switch using the ANALOG_SW_EN signal to enable the outputs. On the other hand, the VDD levels are potentially beyond the allowed voltage for the analog switch so we use a different set of components to enable and disable these levels. An optical isolator is used to drive the MOSFET switch which when turned on passes the VDD level.

Sheet 4

The top of this sheet shows the spare circuits that are on the board. Note that in the case of spare 1 and spare 2, that a jumpers JP4 and JP6 are provide at the analog switch’s input. These should be installed into the grounded position to keep the spare 1 and spare 2 signals that come through umbilical cable free of noise. Again, the other non-switched spares and returns should similarly jumpered to ground. At the bottom of the sheet, are output connectors P3 and P4. These connectors contain all of the signals and levels that go directly to the CCD plus that lines for the temperature diode and heater resister. P4 to the left contains the clock signals and P3 contains the bias levels. The mates to these connectors are hand-wired twisted pairs with grounds on one side of the connector and the signal on the other side. These are wired to the 61-pin connector that mates with the hermetic connector in the dewar.